Role: Advanced ASIC / FPGA Design Engineer
Location: McLeansville, NC
Rate Range: $50.00 - $61.50/hr W2 hourly contract only with limited-benefits
Must be a United States Citizen to apply.
***No C2C, we can NOT work with outside agencies/vendors, and we can NOT do 1099-
**US CITIZENSHIP IS REQUIRED**
We encourage you to apply if you have any of these preferred skills or experiences:
Experience with VHDL/Verilog/SystemVerilog and TCL or similar languages, Zync UltraScale+ MPSoC or similar FPGAs, Vivado or similar tools.
Seeking an Advanced ASIC / FPGA Embedded Engineer to be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products.
Requirements
- US Citizenship
- Bachelor degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.
- Proficient in the principles and techniques of FPGA design. Keeps abreast of technology trends.
- Proficient written and verbal communications skills, ability to think creatively, and multi-task.
- Proficient skill in communicating issues, impacts, and corrective actions.
- Works under limited direction. Regular contact with senior levels of internal work groups. Contact with project leaders and other professionals within the Engineering department and with project teams across the company. Some contact with external customers.
Preferred Skills
- Experience with Multi-Gigabit Transceivers (MGTs): GTX/GTH/GTY/GTZ/etc…
- Experience with bus protocols like: 1G/10G/40G Ethernet, SONET, OTN, EtherCAT, RS-232, SPI, I2C, and CAN.
- Experience working with time critical or low latency designs with PTP/SyncE or synchronous industrial networks like EtherCAT and Sercos III
- Experience with packet or signal processing
- Experience interfacing to external memory interfaces like: DRAM / SRAM.
- Experience with Zynq processors using Petalinux, Yocto, or Buildroot.
- Experience with Git for version control and CI/CD flows for FPGA.
- Understanding of static timing analysis, timing closure and floor planning techniques for designs that include but are not limited to custom developed solutions with embedded hard & soft processors and with commercial & custom IP.
- Understanding of communication link design: including equalization techniques, FEC, filtering, and clock recovery
Please respond to Meredith Baldwin with your interest level, recent copy of your resume and your availability for a call to Mbaldwin@geologics.com
GeoLogics is an Equal Opportunity/Affirmative Action Employer that is committed to hiring a diverse and talented workforce. EOE/Disability/Veteran